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[VHDL-FPGA-Verilog] VHDL

Description: 自编自写的ＶＨＤＬ代码，用于实现全加器功能，可能有误-, Directed and written in VHDL code, for the realization of full-adder function, may have mistaken
Platform: | Size: 4096 | Author: 金嘉 | Hits:

[VHDL-FPGA-Verilog] fulladder

Description: 全加器,有半加器和或门组成.元件例化语句.-Full adder, half adder and OR gate components. Components of sentence cases.
Platform: | Size: 12288 | Author: 周林 | Hits:

[VHDL-FPGA-Verilog] verilog5

Description: verilog语言中 testbencch编写-仿真工具综合工具使用-全加器实例讲解-Verilog language testbencch preparation- the use of simulation tools integrated tools- examples of full adder on the
Platform: | Size: 189440 | Author: 隋学伟 | Hits:

[VHDL-FPGA-Verilog] full_adder3

Description: 三位全加器的源代码，和测试代码，用Verilog HDL实现的！-The three full adder of the source code, and test code, using Verilog HDL to achieve!
Platform: | Size: 35840 | Author: 陈吉成 | Hits:

[Other] MAXPLUS2

Description: EDA课程所用的Max Plus2软件，制作的半加器，有图像文件，有波形文件，建议看看，-EDA courses used by Max Plus2 software, produced a half-adder, there are image files, documents have waveform, it is recommended to see,
Platform: | Size: 31744 | Author: jimchen | Hits:

[Other] electron

Description: 各种电子器件管脚图,THD-1型数字电路实验箱简介,门电路及参数测试,半加器、全加器,数据选择器,数码比较器,译码器和数码显示器,锁存器和触发器,中规模计数器,双向移位寄存器,三态门和数据总线,半导体存储器,多谐振荡器,单稳态触发器,CMOS门电路及集成施密特触发器,集成数模转换器(DAC),逐次渐进型模数转换器(ADC)-Pin diagram of various electronic devices, THD-1 Digital circuit experiment box profiles, gate circuit and the parameters of testing, half adder, full adder, data selector, a digital comparator, decoder and digital display latch and flip-flops, counter scale, bi-directional shift register, three-state gate and data bus, semiconductor memory, Multivibrator, monostable multivibrator, CMOS gate circuits and integrated Schmitt trigger, integrated digital-analog conversion browser (DAC), successive progressive ADC (ADC)
Platform: | Size: 707584 | Author: zl | Hits:

[VHDL-FPGA-Verilog] f_adder

Description: 用VHDL语言采用串行方法实现用1位全加器实现4位全加器-Using VHDL language using the serial method of using a full adder realize four full adder
Platform: | Size: 195584 | Author: chenli | Hits:

[Windows Develop] 1002016p_Sa

Description: 设计一个两位全加器，并用发光二极管显示结果。全加器的三个输入（二个数字输入，一个进位输入）用实验箱中W1,SW2,SW3控制，二个输出用发光管LED1,LED2显示。整个设计采用层次设计方法，顶层文件采用原理图输入法。整个电路设计思路分三部分： 1半加器电路设计； 2.全加器电路设计，是在半加器的基础上设计的； 3.数据输入，输出电路设计。 -The design of a two full-adder, and the result will be displayed using light-emitting diodes. Full adder of the three inputs (two digital input, a binary input) with the experimental box W1, SW2, SW3 control, two output with LED LED1, LED2 display. Used throughout the design-level design methodology, the top-level schematic document using the input method. The whole circuit design divided into three parts: one half adder circuit design 2. Full adder circuit design, in the half adder based on the design 3. Data input and output circuit design.
Platform: | Size: 34816 | Author: chenli | Hits:

[MPI] VHDL_add_4

Description: 本程序完成带进位输入输出的四位二进制加法运算，编程思想采用真值表转换成布尔方程式，利用循环语句将一位全加器编为四位加法器。-This procedure is completed into the four-bit input and output binary adder computing, programming thinking of using truth table into a Boolean equation using a loop will be as full adder adder 4.
Platform: | Size: 94208 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] Project_Navigator_Demo

Description: 双向控制全加器的VHDL实现 内含ISE工程文件-Bi-directional control of the full adder VHDL realize intron ISE project file
Platform: | Size: 109568 | Author: 301z | Hits:

[Other] Example-3-1

Description: 该程序是用quartus II作为开发工具，用verilog语言编写，实现全加器功能的实例。对初学者很有意义-The program is used as a quartus II development tools, using Verilog language, the realization of full-adder function example. Meaningful for beginners
Platform: | Size: 1024 | Author: xyq | Hits:

[VHDL-FPGA-Verilog] Full_Adder

Description: 用VERILOG语言实现了全加器,可综合可仿真通过-Verilog language used to achieve the full adder can be integrated to simulation through
Platform: | Size: 71680 | Author: zhuangqi | Hits:

[VHDL-FPGA-Verilog] chap8

Description: 常用经典典型电路，如全加器，乘法器，如何减小资源-Commonly used classical typical circuit, such as the full adder, multiplier, how to reduce the resources
Platform: | Size: 4096 | Author: 王鹏 | Hits:

[assembly language] VHDLquanjiaqi

Description: 这是一个利用MAX PULL 制作的VHDL的全加器的程序 如果有需要仿真图的 请叫站长联系我-This is a MAX PULL produced using the full adder VHDL process simulation map, if necessary please contact me call station
Platform: | Size: 1024 | Author: 郭明磊 | Hits:

[assembly language] VHDLsiweiquanjiaqqi

Description: 这是一个利用MAX PULL 制作的VHDL的四位全加器的程序 如果有需要仿真图的 请叫站长联系我-This is a MAX PULL using VHDL produced four full-adder process simulation map, if necessary please contact me call station
Platform: | Size: 1024 | Author: 郭明磊 | Hits:

[source in ebook] vhdl

Description: 半加器 或门 1位二进制全加器顶层设计描述-Half adder or a binary gate full adder top-level design description
Platform: | Size: 1024 | Author: chengfeng | Hits:

[VHDL-FPGA-Verilog] adder1

Description: 一个全加器的VHDL程序,经过编译和仿真.-A full adder of the VHDL program, after compiling and simulation.
Platform: | Size: 152576 | Author: 何情 | Hits:

[VHDL-FPGA-Verilog] 1

Description: 基于eda中vhdl语言的一位全加器的设计，详细的设计过程和实验现象，相互学习-Based on EDA VHDL language in a full adder design, detailed design process and the experimental phenomena and learn from each other
Platform: | Size: 859136 | Author: 原来 | Hits:

[Other] ADDER4B

Description: 此程序是用VHDL硬件描述语言编写的,实现四位全加器的功能-This procedure is used VHDL hardware description languages, the realization of the four full-adder function
Platform: | Size: 53248 | Author: | Hits:

[VHDL-FPGA-Verilog] 1

Description: 1位全加器的vhdl设计 通过两个半加起实现-A full adder of VHDL design increases since the adoption of two and a half to achieve
Platform: | Size: 111616 | Author: xiaobai | Hits:
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